In general, a semiconductor device receives a power voltage (VDD) and a ground voltage (VSS) from an outside and generates and uses an internal voltage required in an internal circuit. The voltage required in the internal circuit of the semiconductor memory device includes, a core voltage (Vcore) supplied to a memory core region, a high voltage (Vpp) used upon driving of a word line or overdriving, and a back bias voltage (VBB) supplied as a bulk voltage of an NMOS transistor in the core region.
Meanwhile, a mobile device such as a mobile phone, a portable multimedia player (PMP) and a notebook computer is easily carriyable and can be used during travel, but has a limited operation time due to limitation in a battery capacity. Therefore, in order to lengthen the operation time of the mobile device, there have been tried various attempts for current consumption in a semiconductor memory device used in the mobile device (hereinafter, referred to as a ‘mobile semiconductor memory device’).
Among such attempts, there is a method of reducing the current consumption in a standby mode in which an actual operation such as read operation and write operation is not performed and command standby state is maintained, which will be described with reference to FIG. 1.
As illustrated in FIG. 1, a conventional semiconductor memory device is provided with a power switch 10 which receives a standby signal STB enabled to a low level in a standby mode and controls supply of a power voltage VDD to an internal circuit 12. The semiconductor with such configuration interrupts the supply of the power voltage VDD to the internal circuit 12 in the standby mode to reduce the current consumption.
However, if the supply of the power voltage VDD is interrupted through the power switch 10 in the standby mode, an input node of the internal circuit 12 is floated and it is thus impossible to exactly confirm the voltage supplied to the internal circuit 12 and unnecessary leakage current can be generated. Also, in a case that a PMOS transistor of an inverter included in the internal circuit 12 receives the power voltage VDD as a bulk voltage, the voltage of the node floated in the standby mode is supplied as the bulk voltage of the PMOS transistor, thereby capable of causing latch-up.